QualificationsCC++FPGADigital designComputer visionBachelor’s degreeMaster’s degree
Contribute to scalable architecture and µArchitecture designs for low-power graphics IP design.
Drive the top-level µArchitecture definition and develop the necessary RTL.
Drive the chip-level integration, verification plan development and verification.
Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
Contribute to ASIC digital µArchitecture, design and verification.
Support the test program development, chip validation and chip life until production maturity.
Work with FPGA engineers to perform early prototyping.
Support hand-off and integration of blocks into larger SOC environments.
Assist with performance/power analysis of IP models.
2+ years of experience as a Digital Design Engineer and/or a Chip Lead.
Experience in RTL coding, synthesis and/or SoC Integration.
Experience in digital design µArchitecture.
Experience with at least 1 procedural programming language (C, C++, Python etc.).
Bachelor’s in Electrical Engineering/Computer Science or equivalent experience.
Experience with Machine learning, graphics or computer vision accelerators.
SystemVerilog OVM/UVM experience.
Experience in SoC integration and ASIC architecture.
Experience with low power design and optimization.
Experience with design synthesis and timing optimization.
Master’s degree in Electrical Engineering/Computer Science.
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