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Google Looking for ASIC Design Engineer, Machine Learning Accelerators at Sunnyvale, CA Full Time
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 2 years of experience in ASIC hardware.
- Experience in logic design, and functional and Power Performance Area (PPA) closure.
- Experience with engineering practices (e.g., code review, testing, refactoring, etc.) and computer architecture.
Preferred qualifications:
- Master’s degree or PhD in Electrical Engineering or Computer Science.
- Experience with one or more successful ASIC products from concept to silicon.
- Knowledge of machine learning.
- Solid understanding of computer architecture, memory subsystem architecture, and/or power management logic.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As an ASIC Design Engineer, you will be part of a team developing Application Specific Integrated Circuits (ASIC) used to accelerate Machine Learning (ML) computation in data centers. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Define micro-architecture specifications.
- Take ownership of one or more modules and implement Register-Transfer Level (RTL).
- Converge functionality and PPA of the design.
- Create simple test benches and debug complex logic simulations.
- Contribute to design methodology, libraries, and code review.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
