Job DetailsFull-timeEstimated: $100,000 – $150,000 a year11 hours ago
Experience in design and analysis of power management IPs, clock, reset, and power sequencing interactions, low power digital ASIC including UPF/CPF.
Experience in multi-voltage domains, power gating, on chip power management, and post-silicon validation and debug.
Experience in Verilog, SystemVerilog, and RTL simulation.
Experience with C/C++, scripting with Tcl, Python, or Perl, gate-level SPICE simulations, and statistical SPICE models.
Experience using EDA tools such as Conformal LP, Power-Artist, DC/RC, PT/PTPX, and/or Incisive/VCS.
Understanding of ASIC design flows and methodology, RTL, verification, synthesis, STA, and formal verification.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a Power Engineer, you will be working to architect power solutions. You will define and drive the power management and optimization methodology from architecture to implementation and sign-off.
You will define the requirements for power management IPs and be responsible for the design, integration, and post-silicon validation. You will set power budgets for use cases and provide power estimation. You will collaborate with cross-functional teams to drive power reduction across the platform.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Define and drive power methodology for design, verification, and implementation of SoCs, and define and develop generic power management IPs to drive clock, reset, and power controls.
Develop methodology and tools for implementing power reduction. Work with tool vendors to address any power-related tool or flow issues.
Work with architects and logic designers to understand the power requirements and define all power specs and budgets.
Verify and approve block and full-chip power intent using EDA tools. Define and develop innovative schemes to achieve power reduction from circuit to system level.
Estimate power for blocks and top-level using EDA tools and roll-up full-chip power.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.