Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
Experience in post-silicon power calibrations and debugs.
Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
Knowledge and experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, and Incisive/VCS.
Proficiency in scripting languages (e.g. Tcl, Python, Perl).
About the job
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
As an ASIC Power Methodology Engineer, you will be part of our Design and Technology Enablement Team where you will be working on next generation technology enablement and exploration for our future products. You will be working on assessing multiple foundry technology nodes and defining future product design implementation strategies and techniques to realize the best Product Privacy Assessment (PPA) in our products.
In this role, you will develop and refine the sign-off and correlation methodology pertaining to power analysis. You will work side by side with architecture, logic design and DFT teams to ensure our chip implementation delivers the best PPAC. You will drive deployment of power methodologies with the implementation team and technology teams. You will develop physical design methodologies, automation scripts, work on technology test chip implementation and write documentation.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Estimate power for IP blocks and top-level and roll-up full-chip power and sign-off on block and full-chip level.
Develop accurate power and performance models for our SoCs, and drive silicon analysis and model correlation to assist power management software.
Develop methodology and tools for implementing power reduction, and work with tool vendors to address any power-related tool or flow issues.
Develop power sign-off methodology and flow to verify low power implementation.
Work with architects, logic and circuit, and physical designers to understand the power requirements and define all power specs and budgets, and drive power reduction initiatives.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.