QualificationsSystem designBachelor’s degree
Bachelor’s degree in Electrical, Electronic, or Computer Engineering, a related field, or equivalent practical experience
7 years of experience in silicon bring up and diagnosis of memory Built-In Self Test (BIST), stuck-at/at-speed transition delay fault model test patterns
Experience with bench-level debug, using instruments such as oscilloscopes/logic analyzers, and collecting Shmoo data
Familiarity with DFT concepts and and understanding of operation of test logic and various diagnosis techniques for memory and logic failures
Familiarity with DFT tools for both Memory Built-In Self Test (MBIST) and Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPG) based test patterns
Familiarity with IEEE and JTAG based protocols and ICL/PDL based test patterns and retargeting flow
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a member of the Design for Test (DFT) Productization team in the Product and Test Engineering organization, you will be responsible for bring up and diagnosis tasks for structural patterns both on Automatic Test Equipment (ATE) and on the bench. Our goal is to resolve all test patterns related issues with a quick turnaround time and minimize the number of iterations needed to make test patterns production worthy. Your work will also involve developing techniques for memory/logic diagnosis, using bench-level debug infrastructure to extract the memory bitmap and logic callouts, and support all return merchant authorization (RMA) debug and yield improvement tasks.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Develop automation to perform diagnosis for both logic and memory failures based on the ATE fail data logs.
Perform detailed analysis of memory failures and generate memory bitmaps and physical coordinates.
Perform layout aware diagnosis of logic failures and generate accurate callout information with defect Pareto principles for driving root cause with the DFT/Design and Failure Analysis teams.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.