Google Looking For Power Architecture and Design Engineer, Accelerator ASIC at Sunnyvale, CA Full Time

Minimum qualifications:
Bachelor’s degree in Electrical Engineering, a related field, or equivalent practical experience

3 years of experience in logic design, post-silicon debug, and/or timing/power closure

Experience in cross-functional contributions in areas outside design, such as test writing, post-silicon data collection, and pre-silicon modeling

Experience in low-power design techniques

Preferred qualifications:
Master’s degree or PhD in Electrical Engineering and Computer Science (EECS), or a related field

5 years of experience in Application Specific Integrated Circuit (ASIC) design

Experience in developing chip-wide power architecture and/or design

Experience with pre-silicon and post-silicon power correlation and power measurement techniques in a lab setup

Understanding of techniques such as Dynamic Voltage Frequency Scaling (DVFS), Turboing, Thermal Management, and Firmware based Power Management

Understanding of high-power processors, system software architectures, and modeling of power, including conducting power performance trade-offs, with knowledge of data analysis packages such as Pandas and NumPy

About the job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Perform architect on power management solutions for improving performance, power, and Total Cost of Ownership (TCO)

Develop architecture and microarchitecture specifications as needed

Tune power management algorithms for optimal product trade-offs

Drive power correlation between pre-silicon and post-silicon to make the right trade-offs for power and performance while developing micro-benchmarks

Be able to understand workloads, rack-scale computing, TCO, and invent solutions that move Google AI solutions to be more effective and efficient

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.