Log In
Sign Up
Google Looking for Senior Power Management Modeling Architect, Silicon at Taipei, Taiwan Full Time
Google welcomes people with disabilities.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, or equivalent practical experience.
- 5 years of experience in power management or firmware development.
Preferred qualifications:
- Advanced degree in Electronics, Computer Engineering, Computer Science, with an emphasis on computer architecture, performance, and power analysis.
- 3 years of experience in people management and developing employees.
- Experience with modeling and validation in TLM environments such as SystemC or Gem5.
- Experience with power management drivers development.
- Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation.
- Knowledge of software and architectural design decisions on power and thermal behavior of the system such as thermal mitigation and scheduling, and cross-layer policy design.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
- Define ASIC power management architecture details for an ASIC that includes functions (i.e., image compute, CPU/GPU) for maximum performance under power and thermal constraints.
- Create and maintain software C-models for the next generation SoC power management system applicable at different design levels.
- Implement, model, analyze and test the performance of power management solutions on C-models.
- Produce detailed documentation for the proposed implementation of power management schemes. Produce detailed trade-off analysis for engineering reviews and product roadmap decisions.
- Collaborate with software and the power architecture team to build system level designs and methods.