Job DescriptionIntel Silicon Photonics Product Division (SPPD) is at the forefront of silicon photonics integration and is part of The Connectivity Group which is at the heart of Intel’s transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. Since announcing the world’s first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center bandwidth growth with smaller form factors, co-packaging and higher speeds from 400G today to 1.6T+ and beyond tomorrow. We are looking for great talent to accelerate this journey so if you are interested in joining our leading organization then we want to hear from you.In this role, the Senior Digital IC Design Engineer/Architect will be part of team contributing to Silicon Photonics Solution Group’s mission to transform and lead datacenter connectivity and enable Intel’s differentiation in the networking space. As Senior Engineer, the individual will be involved in developing key digital and mixed signal designs from architecture to product.QualificationsResponsibilities� As part of the team developing key components the engineer must be able to work collaboratively leading block level and chip-level digital IC development � Determines creative design approaches and parameters.� Analyzes equipment to establish operating data. � Conducts experimental tests and evaluates results.� Applies and uses independent evaluation to selects components and equipment based on analysis of specifications and reliability.� Evaluates practical capability of vendor to support product development. Minimum QualificationsThe ideal candidate should have MS in Electrical Engineering or Computer Engineering. 5+ years of experience in SerDes / micro-controller High Speed Digital Development.� Create DSP/FEC hardware block specifications appropriate for RTL implementation� Experience in the design of the Mixed-Signal or DSP based multi-Gb/s SerDes� Experience, projects in or familiar with physical layer algorithms and standards, in the field of SerDes,� Expert knowledge in Communication Theory and Digital Signal Processing algorithms.� Good understanding of how DSP algorithms map onto efficient hardware designs� Able to Lead the design team through various phases of the ASIC/SOC design process – Product definition, Architecture, RTL design using Verilog, system Verilog, verification, syntheses, PnR and STA.� Must be hands-on and possess solid design and architecture experience for chip and system definition, low power design techniques, multiple power domain design, clock gating, multi-VT design, DFx, CPF and CDC tools.� Support product validation, ATE test and QUAL teams during high volume ramp-up.� Deep knowledge of CMOS/BiCMOS Process in 90nm, 45nm and 28nm.� Experience with integrated analog mixed signal designs.� Good understanding of low noise PLL, Clocking and data recovery architectures.� Good understanding of Signal Integrity and Channel modeling.� Experienced with Digital and Mixed signal design flow using Synopsys, Cadence and Mentor tools.� Excellent oral and written communication skills.Preferred Qualifications� Experience in designing high-speed digital Clock and Data Recovery (CDR) is a plus.� Knowledge of IEEE 802.3 10G/25G/50G Serdes is a plus� Deep understanding of full-chip designs including custom IO and package design.� Familiarity with Optical communications. � Experience in designing circuits for 28Gbps+ operation. � Experience with Modulation techniques such as NRZ/PAM4 SERDES and system standards such as CAUI-4 or OIF-25G-VSR.Inside this Business GroupThe focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center. Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.htmlIt has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.Working ModelThis role will require an on-site presence.